By Daniel J. Sorin, Mark D. Hill, David A. Wood
Many glossy desktops and so much multicore chips (chip multiprocessors) help shared reminiscence in undefined. In a shared reminiscence method, all of the processor cores may possibly learn and write to a unmarried shared tackle house. For a shared reminiscence computing device, the reminiscence consistency version defines the architecturally seen habit of its reminiscence process. Consistency definitions supply ideas approximately quite a bit and shops (or reminiscence reads and writes) and the way they act upon reminiscence. As a part of assisting a reminiscence consistency version, many machines additionally offer cache coherence protocols that make sure that a number of cached copies of knowledge are stored updated. The target of this primer is to supply readers with a uncomplicated realizing of consistency and coherence. This knowing contains either the problems that has to be solved in addition to quite a few suggestions. We current either highlevel options in addition to particular, concrete examples from real-world platforms. desk of Contents: Preface / creation to Consistency and Coherence / Coherence fundamentals / reminiscence Consistency Motivation and Sequential Consistency / overall shop Order and the x86 reminiscence version / cozy reminiscence Consistency / Coherence Protocols / Snooping Coherence Protocols / listing Coherence Protocols / complicated themes in Coherence / writer Biographies
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Additional info for A Primer on Memory Consistency and Cache Coherence
Flashback to Quiz Question 1: In a system that maintains sequential consistency, a core must issue coherence requests in program order. True or false? Answer: False! A core may issue coherence requests in any order. Dynamically Scheduled Cores Many modern cores dynamically schedule instruction execution out of program order to achieve greater performance than statically scheduled cores that must execute instructions in strict program order. A single-core processor that uses dynamic or out-of-(program-)order scheduling must simply enforce true data dependences within the program.
Coherence will make all caches invisible, but the stores are already NEW. Nevertheless, r2 can be 0 in some of today’s computer systems. reordered. Hardware can make r2 get the value 0 by re-ordering Core C1’s stores S1 and S2. , if we Load-load reordering. Modern dynamically-scheduled cores may execute instructions out look only C1’s execution do not consider with other threads), of at program order. 1, Core C2 could execute loadsthis L1reordering and L2 outseems of cororder. S1 Considering only adifferent single-threaded execution, this reordering seems safe because L1the andways in rect, because and S2 access addresses.
Ranganathan, V. S. Pai, and S. V. Adve. Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models. In Proceedings of the Ninth ACM Symposium on Parallel Algorithms and Architectures, pp. 199–210, June 1997. 258512 A. Roth. Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization. In Proceedings of the 32nd Annual International Symposium on Computer Architecture, June 2005. 48 D. Shasha and M. Snir. Efficient and Correct Execution of Parallel Programs that Share Memory.